1. Field of the Invention
The present invention relates to the technical field of memory accesses and, more particularly, to an apparatus and method for data strobe and timing variation detection of an SDRAM interface.
2. Description of Related Art
With the rapid advance of computer systems, microcomputer systems, consumer electronics and semiconductor technologies, the audio-visual performance of electronic products has significantly developed. Therefore, the data source synchronous communication interfaces have relatively advanced. For example, the access speed of synchronous dynamic random access memory (SDRAM), such as DDR, DDR2 and DDR3, is rapidly increased to thereby provide a higher memory bandwidth. The SDRAM access speed is improved from xMHz few years ago to xGHz nowadays. Accordingly, more sophisticated mechanism, method and circuit are required for accurately reading data, and a more complete scheme is required for handling the synchronous control between chips, detecting the timing variation and performing the regulation mechanism, so as to surely obtain the system stability and reliability.
The SDRAM device is essentially used as a working memory for a computer system, and the technical feature is to use a data source synchronous interface protocol. The SDRAM data transfer is essentially relied on a common clock signal and data strobe signal (DQS) as a reference to complete the signal synchronization and the synchronous data latch and transmission.
The data strobe signal is a control signal allowing a data receiving side to latch data on a data bus. A typical way uses an internal clock of the data receiving side to pass the data strobe signal through a gated circuit to produce an effective data strobe signal, then performs a phase delay operation on the effective data strobe signal, and finally latches the data with respect to the rising edges and falling edges of the delayed data strobe signal. Typically, the data bus is an 8-bit data bus.
A system with an SDRAM device needs a memory controller to issue relative commands and data to the SDRAM device to complete a SDRAM access task. For a write command execution, the memory controller issues a serial of command (pre-charge, active and write) to the SDRAM interface and then drives the write data (DQ), differential data-strobe-signal (DQS, DQS_B) and data_mask signals (DM) to SDRAM interface. For a read command execution, the memory controller issues a serial of command (pre-charge, active and read) to the SDRAM interface, and after a plurality of clock cycles, the SDRAM device is based on the timing specification to output pairs of read data and data-strobe signals on synchronous communication interface (DQ, DQS, DQS_B).
The interface timing delay certainly occurs in a synchronous interface on physical path and operation of the high-speed data transmission interface. The timing delay is from a transistor's operation time, a transmission line's propagation/transition delay and the like. In case the phases of data strobe signal and data bus signal are same delay value and have a have a reference synchronous clock signal (CKP and CKN), therefore a data source synchronous interface technology can be applied to a very high speed system. In addition, for reducing the amount of synchronous interface signals as best as possible, the data strobe signal and the data bus signal are designed in bi-direction in the DDR SDRAM interface.
Upon the SDRAM interface standard, multiple control signals are used to perform the SDRAM access command operations, and the used control signals include clock (CKP & CKN), row address strobe (RAS_B), column address strobe (CAS_B), write enable (WE_B) and address bus signals.
The following is a basic operation and corresponding interface signal transmission for an SDRAM read command. The SDRAM controller first sends a read command to the SDRAM interface based on a defined timing specification. After certain clock cycles, the SDRAM device refers to the phase of a clock signal to output data on synchronous data bus signals (DQ) and data strobe signals (DQS). The data bus and data strobe signals are connected to memory controller through a PCB, to IO PADs and then to the data receiving circuit of memory controller.
A high speed system requires a quite accurate clock phase control circuit to control the phase/timing of a data strobe signal and data bus. The data receiving device necessarily estimates the arrival time of data outputted by a data transfer device for receiving the data. However, the synchronous data bus signal and the data strobe signal are sent to the corresponding pins of the data receiving device through the transmission line and to the data receiving circuit through the I/O pads. The referred clock signal for the synchronous data communication system is for the SDRAM controller and SDRAM device. The synchronous clock signal is driven by SDRAM controller and use the signal timing to output signals and expected the input signal's timing. The SDRAM device accordingly the referred clock signal to drive signals (DQ, DQS) on the SDRAM interface.
In practice, the characteristic variation of chip processing, the feature of PCB, the temperature variation of chip and system, and the voltage variation of chip and system will influence the delayed amount on signal transmission of the synchronous data interface. Accordingly, the signal cannot accurately arrive at the data receiving side on the expected time slot. Particularly, when the timing variation is overlarge, the data cannot be latched correctly at the data receiving side. The techniques to control the timing and detect and regulate the timing variation are very important mechanism for a data source synchronous interface.
The conventional skill directly uses a gated circuit to process the data strobe signal at the data receiver. The data receiving side uses the expected cycle number and phase control circuit to generate the data valid signal. The SDRAM controller will use the data valid signal to perform a signal gated/mask process on the externally coming data strobe signal for producing a safe data strobe signal without any glitch, wherein the most difficulty is to properly estimate the correct timing of the data strobe signal. When the operation speed of the synchronous signal interface increases more and more, the difficulty in properly estimating the correct timing of the valid data strobe signal is relatively increased a lot. If the possible timing variation is concurrently considered, since the time of data arrival cannot be estimated properly or the timing of the gate circuit cannot be detected and regulated effectively, the design with the conventional circuit has a glitch signal contributed to the internal data strobe signal to thereby cause an incorrect data latch.
U.S. Pat. No. 6,940,760 granted to Borkenhagen, et al. for a “Data strobe gating for source synchronous communications interface” uses a DQS gate circuit to process an externally coming data strobe signal (DQS) to thereby produce a safe DQS without any glitch. FIG. 1 shows a block diagram of an SDRAM controller 40 disclosed in the U.S. Pat. No. 6,940,760. As shown in FIG. 1, the memory controller 40 includes a IO drive/receive circuitry 46, i.e., an SDRAM interface, to drive and receive the data, a DQS gated circuit 52 connected to the SDRAM interface 46 in order to process a data strobe signal (DQS), a DQS delay circuit 54 connected to the DQS gated circuit 52 in order to regulate the delay of the Gated_DQS from the DQS gated circuit 52, and a read dataflow block 50 connected to the DQS delay circuit 54 in order to latch data on the data bus (DQ) according to the Delayed_Gated_DQS signal. However, such a transmission interface is based on the phase of a synchronous clock signal, and its clock signal is produced by the memory controller 40 and outputted to IO drive/receive circuitry, the pads and pins of the I/O drive circuit of the memory controller 40 to SDRAM device through the PCB, pins and pads of SDRAM device and then to the internal control circuit of the SDRAM device. Finally, the internal control circuit of the SDRAM device sends the data and a data strobe signal to the IO driver/receiver circuitry 46, but the timing of which has a delay/variation compares with ideal case without physical delay and timing variation environment. Namely, the memory controller 40 uses the internal clock phase to produce the control signal for the DQS gate circuit 52, meanwhile, the read data strobe signal has a considerable time delay and phase difference with the internal clock of the memory controller 40. Therefore, such a way is unsafe for producing an effective data strobe signal to perform a data latch, and prone to producing an incorrect timing. In addition, the performance frequency of the entire system is limited by the time delay produced by the IO drive/receive circuitry and the PCB transition lines, so the system cannot be used in current and future high-speed data transmission interface.
Therefore, it is desirable to provide an improved apparatus and method to mitigate and/or obviate the aforementioned problems.